Transistor size optimization in the tailor layout system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
DAC '98 Proceedings of the 35th annual Design Automation Conference
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
On the global fanout optimization problem
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Low Power Oriented CMOS Circuit Optimization Protocol
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
JiffyTune: circuit optimization using time-domain sensitivities
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast and exact transistor sizing based on iterative relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Critical path selection for performance optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Due to the development of high performance portable applications associated to the high-density integration allowed by deep submicron processes, circuit optimization under delay constraints has emerged as a critical issue for VLSI designers. The objective of this work is to avoid the use of random mathematical methods (very CPU time expensive), by defining simple, fast and deterministic indicators allowing easy and fast implementation of circuits at the required speed. We propose to extend the method of equal sensitivity, previously developed for combinatorial paths [1], to circuit sizing in order to solve the circuit convergence branch problem. We propose a coefficient based approach to solve the divergence branch problem. Validation is given by comparing with an industrial tool the performance of different benchmarks implemented in a standard 180nm CMOS process.