Efficient algorithms for extracting the K most critical paths in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Interleaving buffer insertion and transistor sizing into a single optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
POPS: A tool for delay/power performance optimization
Journal of Systems Architecture: the EUROMICRO Journal - Modern methods and tools in digital system design
Transition time modeling in deep submicron CMOS
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Critical path selection for performance optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Speed indicators for circuit optimization
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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Low power oriented circuit optimization consists in selecting the best alternative between gate sizing, buffer insertion and logic structure transformation, for satisfying a delay constraint at minimum area cost. In this paper we used a closed form model of delay in CMOS structures to define metrics for a deterministic selection of the optimization alternative. The target is delay constraint satisfaction with minimum area cost. We validate the design space exploration method, defining maximum and minimum delay bounds on logical paths. Then we adapt this method to a "constant sensitivity method" allowing to size a circuit at minimum area under a delay constraint. An optimisation protocol is finally defined to manage the trade-off performance constraint - circuit structure. These methods are implemented in an optimization tool (POPS) and validated by comparing on a 0.25µm process, the optimization efficiency obtained on various benchmarks (ISCASý85) to that resulting from an industrial tool.