A delay model for logic synthesis of continuously-sized networks
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Wireplanning in logic synthesis
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Gradient-based optimization of custom circuits using a static-timing formulation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Integration, the VLSI Journal - Special issue on timing closure
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Uncertainty-aware circuit optimization
Proceedings of the 39th annual Design Automation Conference
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Wireplanning is an approach in which the timing of input-output paths is planned before modules are specified, synthesized or sized. If these global wires are optimally segmented and buffered, their delay is linear in the path length and independent of the position of the modules along these paths. From timing requirements, the total budget left to modules after allocating the appropriate delay to the wires can be determined. This paper describes how this budget can be optimally divided amongst the modules. A novel, static timing-like, mathematical programming formulation is introduced such that the total module area is minimized. Instead of only the worst delay, all pin-to-pin delays are implicitly taken into account. If area-delay tradeoffs are convex, a reasonable approximation in practice, the program can be solved efficiently. Further, efficiency of different formulations is discussed, and a low-cost method of making the budget relatively immune to downstream uncertainties and surprises is presented. The efficiency of the formulation is clear from benchmarks with over 2000 nodes and 5e19 paths.