IEEE Transactions on Computers
DAC '98 Proceedings of the 35th annual Design Automation Conference
Efficient algorithms for optimum cycle mean and optimum cost to time ratio problems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Classical floorplanning harmful?
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Performance analysis and optimization of latency insensitive systems
Proceedings of the 37th Annual Design Automation Conference
A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Introduction to Algorithms
Proceedings of the 2004 international symposium on Physical design
A method for correcting the functionality of a wire-pipelined circuit
Proceedings of the 41st annual Design Automation Conference
Retiming for Wire Pipelining in System-On-Chip
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
ACG-Adjacent Constraint Graph for General Floorplans
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Physical placement driven by sequential timing analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Interconnect estimation without packing via ACG floorplans
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploiting local logic structures to optimize multi-core SoC floorplanning
Proceedings of the Conference on Design, Automation and Test in Europe
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The performance of a sequential system is usually measured by its frequency. However, with the appearance of global interconnects that require multiple clock periods to communicate, the throughput is usually traded-off for higher frequency (for example, through wire pipelining or latency insensitive design). Therefore, we propose to use the processing rate, defined as the amount of processed inputs per unit time, as the performance measure. We show that the minimal ratio of the flip-flop number over the delay on any cycle is an upper bound of the processing rate. Since the processing rate of a sequential system is mainly decided by its floorplan when interconnect delays are dominant, the problem of floorplanning for processing rate optimization is formulated and solved. We optimize the processing rate bound directly in a floorplanner by applying Howard's algorithm incrementally. Experimental results confirm the effectiveness of our approach.