Linear programming and network flows (2nd ed.)
Linear programming and network flows (2nd ed.)
Introduction to algorithms
Efficient algorithms for optimum cycle mean and optimum cost to time ratio problems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Performance analysis and optimization of latency insensitive systems
Proceedings of the 37th Annual Design Automation Conference
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
Optimal buffered routing path constructions for single and multiple clock domain systems
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Concurrent flip-flop and repeater insertion for high performance integrated circuits
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Asynchronous Wrapper for Heterogeneous Systems
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Retiming for Wire Pipelining in System-On-Chip
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Microarchitecture-aware floorplanning using a statistical design of experiments approach
Proceedings of the 42nd annual Design Automation Conference
Exploiting level sensitive latches in wire pipelining
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Microarchitecture evaluation with floorplanning and interconnect pipelining
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Processing Rate Optimization by Sequential System Floorplanning
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Clustering for processing rate optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Design closure driven delay relaxation based on convex cost network flow
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Using functional independence conditions to optimize the performance of latency-insensitive systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A general model for performance optimization of sequential systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Clustering for processing rate optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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As across-chip interconnect delays can exceed a clock cycle, wire pipelining becomes essential in high performance designs. Although it allows higher clock frequencies, it may change the microarchitecture altogether because of the arbitrary increase in the latencies of the paths and cycles of the circuit. This paper proposes a method to regain the functionality of a wire-pipelined circuit. In this approach, increased cycle latencies are compensated by slowing down the issue rate of the inputs. Our method finds the optimal value of the slowdown required for a circuit as it directly affects the throughput of the circuit. We also incorporate area minimization in our formulation to minimize the number of extra flip-flops added to the circuit. The formulation is tested on circuits derived from ISCAS benchmarks and the results suggest that wire pipelining increases the overall throughput in most of the cases.