Design and Analysis of Power Integrity in Deep Submicron System-on-Chip Circuits

Authors:
L.-R. Zheng;H. Tenhunen
Affiliations:
Department of Electronics, Electronic System Design Laboratory, Royal Institute of Technology, Electrum 229, S-164 40 Kista-Stockholm, Sweden;Department of Electronics, Electronic System Design Laboratory, Royal Institute of Technology, Electrum 229, S-164 40 Kista-Stockholm, Sweden
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2002

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Abstract

This paper proposes a new design methodology and new models for power integrity analysis in deep submicron system-on-chip circuit design. The placement plan and interconnect plan are the first design steps, preceding ia priori signal and power integrity estimations. The initial power distribution is refined progressively from early mode to final placement and layout. In order to improve accuracy and efficiency in early stage estimates, a multilevel dynamic interconnect model and a fast power distribution model are employed, which consequently result in a drastic reduction of the number of iterations through the design cycle. HSPICE simulations verify the efficiency and the accuracy of the method. Finally, some noise-reduced power distribution techniques such as self-decoupling and area array power/ground pin distribution are discussed, and measurement result for effective power distribution is presented.