Design and Analysis of Power Integrity in Deep Submicron System-on-Chip Circuits
Analog Integrated Circuits and Signal Processing
Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Improved a priori terconnect predictions and technology extrapolation in the GTX system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Challenges for architectural level power modeling
Power aware computing
Interconnect-Dominated VLSI Design
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Microarchitectural power modeling techniques for deep sub-micron microprocessors
Proceedings of the 2004 international symposium on Low power electronics and design
An electromigration and thermal model of power wires for a priori high-level reliability prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimizing CMOS technology for maximum performance
IBM Journal of Research and Development - Advanced silicon technology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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