Design methodology for the S/390 parallel enterprise server G4 microprocessors
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Layout techniques for minimizing on-chip interconnect self inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Modeling microprocessor performance
Modeling microprocessor performance
A novel VLSI layout fabric for deep sub-micron applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Interconnect estimation and planning for deep submicron designs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On switch factor based analysis of coupled RC interconnects
Proceedings of the 37th Annual Design Automation Conference
GTX: the MARCO GSRC technology extrapolation system
Proceedings of the 37th Annual Design Automation Conference
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
The interpretation and application of Rent's rule
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
An analytical delay model for RLC interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Equivalent Elmore delay for RLC trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Individual wire-length prediction with application to timing-driven placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimizing CMOS technology for maximum performance
IBM Journal of Research and Development - Advanced silicon technology
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A priori interconnect prediction and technology extrapolation are closely intertwined. Interconnect predictions are at the core of technology extrapolation models of achievable system power, area density, and speed. Technology extrapolation, in turn, informs a priori interconnect prediction via models of interconnect technology and interconnect optimizations. In this paper, we address the linkage between a priori interconnect prediction and technology extrapolation in two ways. First, we describe how rapid changes in technology, as well as rapid evolution of prediction methods, require a dynamic and flexible framework for technology extrapolation. We then develop a new tool, the GSRC technology extrapolation system (GTX), which allows capture of such knowledge and rapid development of new studies. Second, we identify several "nontraditional" facets of interconnect prediction and quantify their impact on key technology extrapolations. In particular, we explore the effects of interconnect design optimizations such as shield insertion, repeater sizing and repeater staggering, as well as modeling choices for RLC interconnects.