Efficient implementation of retiming
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A practical approach to multiple-class retiming
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Integrated retiming and placement for field programmable gate arrays
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
The stratixπ routing and logic architecture
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Incremental placement for layout driven optimizations on FPGAs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Efficient retiming of large circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow
Proceedings of the 2006 international workshop on System-level interconnect prediction
Combinational and sequential mapping with priority cuts
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
An efficient incremental algorithm for min-area retiming
Proceedings of the 45th annual Design Automation Conference
Scalable min-register retiming under timing and initializability constraints
Proceedings of the 45th annual Design Automation Conference
Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Predicting interconnect delay for physical synthesis in a FPGA CAD flow
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we present a new linear-time retiming algorithm that produces near-optimal results. Our implementation is specically targeted at Altera's Stratix [1] FPGA-based designs, although the techniques described are general enough for any implementation medium. The algorithm is able to handle the architectural constraints of the target device, multiple timing constraints assigned by the user and implicit legality constraints. It ensures that register moves do not create asynchonous problems such as creating a glitch on a clock/reset signal.