Introduction to algorithms
IEEE Transactions on Computers
Network flows: theory, algorithms, and applications
Network flows: theory, algorithms, and applications
TIM: a timing package for two-phase, level-clocked circuitry
DAC '93 Proceedings of the 30th international Design Automation Conference
Efficient implementation of retiming
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
DELAY: an efficient tool for retiming with realistic delay modeling
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
A Practical Algorithm for Retiming Level-Clocked Circuits
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Retiming revisited and reversed
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance driven resynthesis by exploiting retiming-induced state register equivalence
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A practical approach to multiple-class retiming
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
The case for registered routing switches in field programmable gate arrays
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Latency and latch count minimization in wave steered circuits
Proceedings of the 38th annual Design Automation Conference
Optimal design of synchronous circuits using software pipelining techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Integrated retiming and placement for field programmable gate arrays
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Optimization of synchronous circuits
Logic Synthesis and Verification
The future of logic synthesis and verification
Logic Synthesis and Verification
UST/DME: a clock tree router for general skew constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Incremental retiming for FPGA physical synthesis
Proceedings of the 42nd annual Design Automation Conference
Clock skew scheduling with race conditions considered
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An efficient incremental algorithm for min-area retiming
Proceedings of the 45th annual Design Automation Conference
Scalable min-register retiming under timing and initializability constraints
Proceedings of the 45th annual Design Automation Conference
iRetILP: an efficient incremental algorithm for min-period retiming under general delay model
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Network flow-based simultaneous retiming and slack budgeting for low power design
Proceedings of the 16th Asia and South Pacific Design Automation Conference
A direct method for optimal VLSI realization of deeply nested n-D loop problems
Microprocessors & Microsystems
The benefits of using variable-length pipelined operations in high-level synthesis
ACM Transactions on Embedded Computing Systems (TECS)
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Retiming, introduced by Leiserson and Saxe, is a powerful transformation of circuits that preserves functionality and improves performance. The ASTRA algorithm proposed an alternative view of retiming using the equivalence between retiming and clock skew optimization and also presented a fast algorithm for minimum period (minperiod) retiming. Since minperiod retiming may significantly increase the number of flip-flops in the circuit, minimum area (minarea) retiming is an important problem. Minarea retiming is a much harder problem than minperiod retiming, and previous techniques were not capable of handling large circuits in a reasonable time. This work defines the relationship between the Leiserson-Saxe and the ASTRA approaches and utilizes it for efficient minarea retiming of large circuits. The new algorithm, Minaret, uses the same basis as the Leiserson-Saxe approach. The underlying philosophy of the ASTRA approach is incorporated to reduce the number of variables and constraints generated in the problem. This allows minarea retiming of circuits with over 56 000 gates in under 15 min.