Efficient implementation of retiming
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Minimum area retiming with equivalent initial states
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Optimizing sequential verification by retiming transformations
Proceedings of the 37th Annual Design Automation Conference
Improving initialization through reversed retiming
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Optimal Retiming for Initial State Computation
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Continuous retiming: algorithms and applications
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Incremental retiming for FPGA physical synthesis
Proceedings of the 42nd annual Design Automation Conference
Fast Minimum-Register Retiming via Binary Maximum-Flow
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Efficient retiming of large circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Retiming revisited and reversed
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal FPGA mapping and retiming with efficient initial state computation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
iRetILP: an efficient incremental algorithm for min-period retiming under general delay model
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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We demonstrate that a maximum-flow-based approach to register-minimization is a useful platform for incorporating varied design constraints. In this work, we extend the flowbased formulation to include timing constraints and to guarantee the existence of an equivalent initial state. Reducing the register count is motivated by positive consequences for physical design, verification, and power consumption, but it is critically necessary for synthesis that these timing and functionality requirements are also met. Our solution is optimum in the number of registers under either or both constraints and also possesses several other distinct advantages: the runtime is significantly faster than comparable techniques, the algorithm is capable of early termination with a timing-feasible solution, and both maximum and minimum path constraints can be specified.