Improved reachability analysis of large finite state machines
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Record & play: a structural fixed point iteration for sequential circuit verification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Using combinational verification for sequential circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Formal implementation verification of the bus interface unit for the Alpha 21264 microprocessor
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Min-area retiming on flexible circuit structures
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Register Transformations with Multiple Clock Domains
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Transformation-Based Verification Using Generalized Retiming
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Enhanced Diameter Bounding via Structural
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Dynamic transition relation simplification for bounded property checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Scalable min-register retiming under timing and initializability constraints
Proceedings of the 45th annual Design Automation Conference
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Sequential verification methods based on reachability analysis are still limited by the size of the BDDs involved in computations. Extending their applicability to larger and real circuits is still a key issue.Within this framework, we explore a new way to improve symbolic traversal performance, working on the representation of state sets. We exploit retiming to reduce the number of latches of a FSM, and to relocate them in order to obtain a simplified state set representation. We consider retiming as a temporary state space transformation to increase the efficiency of sequential verification. We discuss it as a state space transformation and we formally analyze the conditions under which such a transformation is equivalence preserving for a given property under verification.We lower image computation cost, and we reduce the size of BDDs representing intermediate results and state sets. Experimental results show considerable memory and time improvements on some benchmark and home made circuits.