Latency and latch count minimization in wave steered circuits

Authors:
Amit Singh;Arindam Mukherjee;Malgorzata Marek-Sadowska
Affiliations:
Department of Electrical and Computer Engineering, University of California, Santa Barbara, Santa Barbara, CA;Department of Electrical and Computer Engineering, University of California, Santa Barbara, Santa Barbara, CA;Department of Electrical and Computer Engineering, University of California, Santa Barbara, Santa Barbara, CA
Venue:
Proceedings of the 38th annual Design Automation Conference
Year:
2001

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Abstract

Wave Steering is a new design methodology that realizes high throughput circuits by embedding layout friendly synthesized structures in silicon. Wave Steered circuits inherently utilize latches in order to guarantee the correct signal arrival times at the inputs of these synthesized structures and maintain the high throughput of operation. In this paper, we show a method of reor-dering signals to achieve minimum circuit latency for Wave Steered circuits and propose an Integer Linear Programming(ILP) formulation for scheduling and retiming these circuits to minimize the number of latches for minimum latency. Experimental results show that in 0.25mm CMOS technology, as much as 33.2% reduc-tion in latch count, at minimum latency, can be achieved over unoptimized Wave Steered circuits operating at 500 MHz.