Performance-oriented technology mapping
Performance-oriented technology mapping
A near optimal algorithm for technology mapping minimizing area under delay constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
The practical application of retiming to the design of high-performance systems
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Logic synthesis for vlsi design
Logic synthesis for vlsi design
The case for retiming with explicit reset circuitry
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Latency and latch count minimization in wave steered circuits
Proceedings of the 38th annual Design Automation Conference
Integration, the VLSI Journal
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We propose a technology mapping algorithm that takes existing structural technology-mapping algorithms based on dynamic programming and extends them to retime pipelined circuits. If the circuit to be mapped has a tree structure, our algorithm generates an optimal solution compatible with that structure. The algorithm takes into account gate delays and capacitive loads as latches are moved across the logic. It also supports latches with embedded logic: i.e., cells that combine a D latch with a combinational gate at little extra cost in latch delay.