Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
VLSI array processors
Configurable hardware: two case studies of micro-grain computation
Systolic array processors
The triptych FPGA architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logic synthesis for large pass transistor circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Some experiments about wave pipelining on FPGA's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Signal processing at 250 MHz using high-performance FPGA's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
HSRA: high-speed, hierarchical synchronous reconfigurable array
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Wave steering in YADDs: a novel non-iterative synthesis and layout technique
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Clock distribution using multiple voltages
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
The design of a low energy FPGA
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
A novel high throughput reconfigurable FPGA architecture
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Wave-steering one-hot encoded FSMs
Proceedings of the 37th Annual Design Automation Conference
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Interconnect pipelining in a throughput-intensive FPGA architecture
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
The case for registered routing switches in field programmable gate arrays
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Latency and latch count minimization in wave steered circuits
Proceedings of the 38th annual Design Automation Conference
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Wave-pipelining: a tutorial and research survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Valid clock frequencies and their computation in wavepipelined circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we present a novel, high throughput field-programmable gate array (FPGA) architecture, PITIA, which combines the high-performance of application specific integrated circuits (ASICs) and the flexibility afforded by the reconfigurability of FPGAs. The new architecture, which targets datapath circuits, uses the concepts of wave steering and pipelined interconnects. We discuss the FPGA architecture and show results for performance, power consumption, clock network performance, and routability. Results for some commonly used datapath designs are encouraging with throughputs in the neighborhood of 625 MHz in 0.25-µm 2.5-V CMOS technology. Results for random benchmark circuits are also shown. We characterize designs according to their Rent's exponents and argue that designs with predominantly local interconnects are the best fit in PITIA. We also show that as technology scales down toward deep submicron, PITIA shows an increasing throughput performance.