An improved algorithm for minimum-area retiming
DAC '97 Proceedings of the 34th annual Design Automation Conference
Minimum area retiming with equivalent initial states
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Efficient minarea retiming of large level-clocked circuits
Proceedings of the conference on Design, automation and test in Europe
Variables bounding based retiming algorithm
Journal of Computer Science and Technology
Timing optimization by replacing flip-flops to latches
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Efficient retiming of large circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A new approach for fast retiming of level-clocked circuits is presented here. The method relies on the relation between clock skew and retiming, and computes the optimal skew solution to translate it to a retiming. Since clock skew optimization operates on the latches (rather than the gates as in conventional retiming), it is much faster because of a smaller problem size; the translation to the retiming solution is computationally cheap. The minimum period retiming for each of the ISCAS89 circuits was obtained within minutes by this algorithm.