Efficient minarea retiming of large level-clocked circuits

Authors:
N. Maheshwari;S. S. Sapatnekar
Affiliations:
Department of Electrical & Computer Engineering, Iowa State University, Ames IA;Department of Electrical & Computer Engineering, University of Minnesota, Minneapolis, MN
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
1998

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Abstract

Delay-constrained area optimization is an important step in synthesis of VLSI circuits. Minimum area (minarea) retiming is a powerful technique to solve this problem. The minarea retiming problem has been formulated as a linear program; in this work we present techniques for reducing the size of this linear program and efficient techniques for generating it. This results in an efficient minarea retiming method for large level-clocked circuits (with tens of thousands of gates).