Linear programming and network flows (2nd ed.)
Linear programming and network flows (2nd ed.)
Introduction to algorithms
IEEE Transactions on Computers
Efficient implementation of retiming
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
DELAY: an efficient tool for retiming with realistic delay modeling
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A fresh look at retiming via clock skew optimization
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Retiming sequential circuits for low power
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
A Practical Algorithm for Retiming Level-Clocked Circuits
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Retiming revisited and reversed
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Minimum area retiming with equivalent initial states
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Efficient equivalence checking of multi-phase designs using phase abstraction and retiming
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Using combinational verification for sequential circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Retiming sequential circuits with multiple register classes
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A practical approach to multiple-class retiming
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Retiming for DSM with area-delay trade-offs and delay constraints
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Marsh: min-area retiming with setup and hold constraints
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Efficient minarea retiming of large level-clocked circuits
Proceedings of the conference on Design, automation and test in Europe
Optimal design of synchronous circuits using software pipelining techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hardware-Software partitioning and pipelined scheduling of transformative applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Retiming with Interconnect and Gate Delay
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Minimum-Area Sequential Budgeting for FPGA
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Interconnect Planning with Local Area Constrained Retiming
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Simultaneous slack budgeting and retiming for synchronous circuits optimization
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Combining retiming and sequential redundancy addition and removal for sequential logic optimization
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
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The concept of improving the timing behavior of a circuit by relocatingflip-flops is called retiming and was first presented by Leisersonand Saxe. The ASTRA algorithm proposed an alternativeview of retiming using the equivalence between retiming and clockskew optimization. This work defines the relationship betweenthe Leiserson-Saxe and the ASTRA approaches and utilizes it tosolve the problem of retiming for minimum area. The new algorithm,Minaret, uses the linear programming formulation of theLeiserson-Saxe approach. The underlying philosophy of the ASTRAapproach is incorporated to reduce the number of variablesand constraints in the linear program. This reduction in the sizeof the linear program makes Minaret space and time efficient, enablingminimum area retiming of circuits with over 56,000 gates inunder 15 minutes.