On exploring inter-iteration parallelism within rate-balanced multirate multidimensional DSP algorithms

Authors:
Dongming Peng;Mi Lu
Affiliations:
Computer and Electronics Engineering Department, University of Nebraska-Lincoln, Omaha, NE;Electrical Engineering Department, Texas A&M University, College Station, TX
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2005

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Abstract

Although the notion of the parallelism in multidimensional applications has existed for a long time, it is so far unknown what the bound (if any) of inter-iteration parallelism in multirate multidimensional digital signal processing (DSP) algorithms is, and whether the maximum inter-iteration parallelism can be achieved for arbitrary multirate data flow algorithms. This paper explores the bound of inter-iteration parallelism within rate-balanced multirate multidimensional DSP algorithms and proves that this parallelism can always be achieved in hardware system given the availability of a large number of processors and the interconnections between them.