An FPGA power aware design flow

Authors:
David Elléouet;Yannig Savary;Nathalie Julien
Affiliations:
Laboratoire I.E.T.R, UMR CNRS 6164, Institut National des Sciences Appliquées, RENNES, France;Laboratoire L.E.S.T.E.R, FRE CNRS 2734, Université de Bretagne Sud, Lorient, France;Laboratoire L.E.S.T.E.R, FRE CNRS 2734, Université de Bretagne Sud, Lorient, France
Venue:
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2006

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Abstract

Today and more tomorrow, electronic system design requires being concerned with the power issues. Currently, usual design tools consider the application power consumption after RTL synthesis. We propose in this article a FPGA design flow which integrates the power consideration at the early stages. Thus, the designer determines quickly the algorithm and architecture adequacy which respects the design specifications and the power budget.