A new parameterizable power macro-model for datapath components
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Low-energy FPGAs: architecture and design
Low-energy FPGAs: architecture and design
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Interconnect capacitance estimation for FPGAs
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A detailed power model for field-programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Closed-loop modeling of power and temperature profiles of FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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We present our approach for a new macromodule power model library which can be used in high-level dynamic power estimation for FPGA technologies. The approach adapts a previously published high-level estimation flow for ASIC technologies. Due to the different architectures (ASIC vs. FPGA) the presented approach builds on an iterative optimization step during the model generation phase.