Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Flexible Power Model for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Macro-models for high level area and power estimation on FPGAs
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Power estimation techniques for FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Hardware Algorithm for Integer Division
ARITH '05 Proceedings of the 17th IEEE Symposium on Computer Arithmetic
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Power estimation of embedded multiplier blocks in FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analytical estimation of signal transition activity from word-level statistics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We present a methodology for power estimation of non-fractional divider cores implemented in FPGAs. The methodology takes into account the divider structure and the signal statistics at the inputs: mean, variance, and autocorrelation. An analytical model is used for switching activity computation. The strong data dependency observed at the inputs of the divider basic elements is properly modelled in order to improve the model accuracy. The methodology is capable of obtaining fast and accurate estimates when compared to both, real on-board measurements and XPower. The mean relative error is less than 10%, with a maximum error of 22% when estimates are compared to on-board measurements and less than 11% when estimates are compared to low-level estimates provided by the commercial tool.