A new compact SD2 positive integer triangular array division circuit
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power estimation of dividers implemented in FPGAs
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
ACM Transactions on Architecture and Code Optimization (TACO)
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A hardware algorithm for integer division is proposed. It is based on the digit-recurrence, non-restoring division algorithm. Fast computation is achieved by the use of the radix-2 signed-digit representation. The algorithm does not require normalization of the divisor, and hence, does not require area-consuming leading one (or zero) detection nor shifts of variable-amount. Combinational (unfolded) implementation of the algorithm yields a regularly structured array divider, where pipelining is possible for increasing the throughput. Sequential implementation yields a compact divider.