Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor

Authors:
Yohei Hasegawa;Shohei Abe;Shunsuke Kurotaki;Vu Manh Tuan;Naohiro Katsura;Takuro Nakamura;Takashi Nishimura;Hideharu Amano
Affiliations:
Graduate School of Science and Technology, Keio University, Yokohama, Japan;Graduate School of Science and Technology, Keio University, Yokohama, Japan;Graduate School of Science and Technology, Keio University, Yokohama, Japan;Graduate School of Science and Technology, Keio University, Yokohama, Japan;Graduate School of Science and Technology, Keio University, Yokohama, Japan;Faculty of Science and Technology, Keio University, Yokohama, Japan;Faculty of Science and Technology, Keio University, Yokohama, Japan;Faculty of Science and Technology, Keio University, Yokohama, Japan
Venue:
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Year:
2006

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Abstract

Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a datapath called a context from the on-chip repository of sixteen circuit configurations at runtime. The time-multiplexed execution based on the multicontext functionality is expected to drastically improve area and power efficiency. To demonstrate the impact of the time-multiplexed execution, we have implemented several stream applications on DRP with various context sizes. Throughout the evaluation based on real application designs, we analyzed the impact of the time-multiplexed execution on performance and power dissipation quantitatively.