Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor

Authors:
Noriaki Suzuki;Shunsuke Kurotaki;Masayasu Suzuki;Naoto Kaneko;Yutaka Yamada;Katsuaki Deguchi;Yohei Hasegawa;Hideharu Amano;Kenichiro Anjo;Masato Motomura;Kazutoshi Wakabayashi;Takeo Toi;Toru Awashima
Affiliations:
Keio University, Japan;Keio University, Japan;Keio University, Japan;Keio University, Japan;Keio University, Japan;Keio University, Japan;Keio University, Japan;Keio University, Japan;NEC Electronics, Japan;NEC Electronics, Japan;NEC System Devices Research Lab., Japan;NEC System Devices Research Lab., Japan;NEC System Devices Research Lab., Japan
Venue:
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Year:
2004

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Abstract

Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on DRP-1, the first prototype chip, and evaluation results are presented. By computing parallelly using the Processing Elements(PEs) and distributed memory modules, DRP-1 out-performed Pentium III/4 and embedded CPU MIPS64 in some stream application examples. We also present programming techniques applicable on reconfigurable processors and discuss their feasibility in boosting system performance.