Register allocation via graph coloring
Register allocation via graph coloring
DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
New Recursive Algorithms for the Unified Forward and Inverse MDCT/MDST
Journal of VLSI Signal Processing Systems
The MorphoSys Dynamically Reconfigurable System-on-Chip
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture
IEEE Transactions on Computers
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A Wavelet Tour of Signal Processing, Third Edition: The Sparse Way
A Wavelet Tour of Signal Processing, Third Edition: The Sparse Way
IEEE Spectrum
Automated Synthesis of Data Paths in Digital Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Since the introduction of the first reconfigurable devices in 1985 the field of reconfigurable computing developed a broad variety of architectures from fine-grained to coarse-grained types. However, the main disadvantages of the reconfigurable approaches, the costs in area, and power consumption, are still present. This contribution presents a solution for application-driven adaptation of our reconfigurable architecture at register transfer level (RTL) to reduce the resource requirements and power consumption while keeping the flexibility and performance for a predefined set of applications. Furthermore, implemented runtime adaptive features like online routing and configuration sequencing will be presented and discussed. A presentation of the prototype chip of this architecture designed in 90 nm standard cell technology manufactured by TSMC will conclude this contribution.