Performance analysis of dynamic threshold MOS (DTMOS) based 4-input multiplexer switch for low power and high speed FPGA design

Authors:
Deepak Kumar;Pankaj Kumar;Manisha Pattanaik
Affiliations:
ABV- Indian Institute of Information Technology and Management, Gwalior, India;ABV- Indian Institute of Information Technology and Management, Gwalior, India;ABV- Indian Institute of Information Technology and Management, Gwalior, India
Venue:
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Year:
2010

Citing 4
Cited 0

Dynamic power consumption in Virtex™-II FPGA family

FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique

Proceedings of the 39th annual Design Automation Conference
A Flexible Power Model for FPGAs

FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Ultra-low-power DLMS adaptive filter for hearing aid applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents a detailed performance analysis of a 4-input multiplexer switch based on two different dynamic threshold MOS (DTMOS) configurations. Proper and efficient sizing of all the required transistors in the design were done so as to achieve an improved performance in delay and optimum power delay product (PDP). As compared to minimum size DTMOS based multiplexer switch designs, augmenting transistor DTMOS and augmenting fixed reference voltage transistor DTMOS designs shows an improvement of 12.32% and 11.19% in delay as well as 8.29% and 8.26% in optimum power delay product (PDP) for Virtex-4 low cost 90 nm FPGA. Since FPGA consists of thousands of 4-input multiplexers in its design, so an improvement in delay and PDP will be of great significant for low power and high speed FPGA designs.