Multi-port abstraction layer for FPGA intensive memory exploitation applications

  • Authors:

  • M. Vanegas;M. Tomasi;J. Díaz;E. Ros

  • Affiliations:

  • Department of Computer Architecture and Technology, University of Granada, 18071 Granada, Spain and Microelectronic Group, Pontificia Bolivariana University, Medellín, Colombia;Department of Computer Architecture and Technology, University of Granada, 18071 Granada, Spain;Department of Computer Architecture and Technology, University of Granada, 18071 Granada, Spain;Department of Computer Architecture and Technology, University of Granada, 18071 Granada, Spain

  • Venue:
  • Journal of Systems Architecture: the EUROMICRO Journal
  • Year:
  • 2010

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Abstract

We describe an efficient, high-level abstraction, multi-port memory-control unit (MCU) capable of providing data at maximum throughput. This MCU has been developed to take full advantage of FPGA parallelism. Multiple parallel processing entities are possible in modern FPGA devices, but this parallelism is lost when they try to access external memories. To address the problem of multiple entities accessing shared data we propose an architecture with multiple abstract access ports (AAPs) to access one external memory. Bearing in mind that hardware designs in FPGA technology are generally slower than memory chips, it is feasible to build a memory access scheduler by using a suitable arbitration scheme based on a fast memory controller with AAPs running at slower frequencies. In this way, multiple processing units connected through the AAPs can make memory transactions at their slower frequencies and the memory access scheduler can serve all these transactions at the same time by taking full advantage of the memory bandwidth.