A Computational Approach to Edge Detection
IEEE Transactions on Pattern Analysis and Machine Intelligence
Real-time considerations in the design of the image understanding architecture
Real-Time Imaging - Special issue on special purpose architectures for real-time imaging
Introduction to data compression (2nd ed.)
Introduction to data compression (2nd ed.)
Distinctive Image Features from Scale-Invariant Keypoints
International Journal of Computer Vision
A Performance Evaluation of Local Descriptors
IEEE Transactions on Pattern Analysis and Machine Intelligence
Multiscaled Texture Synthesis Using Multisized Pixel Neighborhoods
IEEE Computer Graphics and Applications
Speeded-Up Robust Features (SURF)
Computer Vision and Image Understanding
Image Compression with Anisotropic Diffusion
Journal of Mathematical Imaging and Vision
Short Communication: A method for sparse disparity densification using voting mask propagation
Journal of Visual Communication and Image Representation
Optimization strategies for high-performance computing of optical-flow in general-purpose processors
IEEE Transactions on Circuits and Systems for Video Technology
A compact harmonic code for early vision based on anisotropic frequency channels
Computer Vision and Image Understanding
Using Human Visual System modeling for bio-inspired low level image processing
Computer Vision and Image Understanding
Multi-port abstraction layer for FPGA intensive memory exploitation applications
Journal of Systems Architecture: the EUROMICRO Journal
A Database and Evaluation Methodology for Optical Flow
International Journal of Computer Vision
IEEE Transactions on Computers
Efficient multiscale regularization with applications to the computation of optical flow
IEEE Transactions on Image Processing
IEEE Transactions on Circuits and Systems for Video Technology
Pipelined architecture for real-time cost-optimized extraction of visual primitives based on FPGAs
Digital Signal Processing
Real-time architecture for a robust multi-scale stereo engine on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We describe an intelligent scheme to condense dense vision features, efficiently reducing the size of representation maps and keeping relevant information for further processing during subsequent stages. We have integrated our condensation algorithm in a low-level-vision system that obtains several vision-features in real-time working on an FPGA. Within this framework, our condensation algorithm allows for the transfer of information from the FPGA device (or processing chip) to any co-processor (from embedded ones to external PCs or DSPs) under technological constraints (such as bandwidth, memory and performance ones). Our condensation core processes 1024 脳 1024 resolution images at up to 90 fps. Hence, our condensation module performs this process introducing an insignificant delay in the vision system. A hardware implementation usually implies a simplified version of the vision-feature extractor. Therefore, our condensation process inherently regularizes low-level-vision features, effectively reducing discontinuities and errors. The semidense representation obtained is compatible with mid-/high-level-vision modules, usually implemented as software components. In addition, our versatile semidense map is ready to receive feedback from attention processes, integrating task-driven attention (i.e. top-down information) in real time. Thus, the main advantages of this core are: real-time throughput, versatility, inherent regularization, scalability and feedback from other stages.