Parallel architecture for hierarchical optical flow estimation based on FPGA

Authors:
Francisco Barranco;Matteo Tomasi;Javier Diaz;Mauricio Vanegas;Eduardo Ros
Affiliations:
Department of Computer Architecture and Technology, CITIC, ETSIIT, University of Granada, Granada, Spain;Department of Computer Architecture and Technology, CITIC, ETSIIT, University of Granada, Granada, Spain;Department of Computer Architecture and Technology, CITIC, ETSIIT, University of Granada, Granada, Spain;Department of Computer Architecture and Technology, CITIC, ETSIIT, University of Granada, Granada, Spain and PSPC Group, Department of Biophysical and Electronic Engineering, University of Genoa, ...;Department of Computer Architecture and Technology, CITIC, ETSIIT, University of Granada, Granada, Spain
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2012

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Abstract

The proposed work presents a highly parallel architecture for motion estimation. Our system implements the well-known Lucas and Kanade algorithm with the multi-scale extension for the computation of large motion estimations in a dedicated device [field-programmable gate array (FPGA)]. Our system achieves 270 frames per second for a 640×480 resolution in the best case of the mono-scale implementation and 32 frames per second for the multi-scale one, fulfilling the requirements for a real-time system. We describe the system architecture, address the evaluation of the accuracy with well-known benchmark sequences (including a comparative study), and show the main hardware resources used.