Distributed representation and analysis of visual motion
Distributed representation and analysis of visual motion
Performance of optical flow techniques
International Journal of Computer Vision
Accuracy vs efficiency trade-offs in optical flow algorithms
Computer Vision and Image Understanding
Real-Time Implementation of an Optical Flow Algorithm
ICPR '02 Proceedings of the 16 th International Conference on Pattern Recognition (ICPR'02) Volume 4 - Volume 4
Lucas/Kanade meets Horn/Schunck: combining local and global optic flow methods
International Journal of Computer Vision
Hardware/Software Co-Design of an FPGA-based Embedded Tracking System
CVPRW '06 Proceedings of the 2006 Conference on Computer Vision and Pattern Recognition Workshop
High speed computation of the optical flow
ICIAP'05 Proceedings of the 13th international conference on Image Analysis and Processing
FPGA-based real-time optical-flow system
IEEE Transactions on Circuits and Systems for Video Technology
Proceedings of the 14th international conference on Model driven engineering languages and systems
A multi-resolution approach for massively-parallel hardware-friendly optical flow estimation
Journal of Visual Communication and Image Representation
Optical flow estimation for motion-compensated compression
Image and Vision Computing
Parallel architecture for hierarchical optical flow estimation based on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Real-Time Image Processing
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Optical flow computation in vision-based systems demands substantial computational power and storage area. Hence, to enable real-time processing at high resolution, the design of application-specific system for optic flow becomes essential. In this paper, we propose an efficient VLSI architecture for the accurate computation of the Lucas-Kanade (L-K)-based optical flow. The L-K algorithm is first converted to a scaled fixed-point version, with optimal bit widths, for improving the feasibility of high-speed hardware implementation without much loss in accuracy. The algorithm is mapped onto an efficient VLSI architecture and the data flow exploits the principles of pipelining and parallelism. The optical flow estimation involves several tasks such as Gaussian smoothing, gradient computation, least square matrix calculation, and velocity estimation, which are processed in a pipelined fashion. The proposed architecture was simulated and verified by synthesizing onto a Xilinx Field Programmable Gate Array, which utilize less than 40% of system resources while operating at a frequency of 55 MHz. Experimental results on benchmark sequences indicate 42% improvement in accuracy and a speed up of five times, compared to a recent hardware implementation of the L-K algorithm.