A low level real-time vision system using specific computing architectures
ISCGAV'06 Proceedings of the 6th WSEAS International Conference on Signal Processing, Computational Geometry & Artificial Vision
Reconfigurable hardware implementation of a fast and efficient motion detection algorithm
MMACTEE'08 Proceedings of the 10th WSEAS International Conference on Mathematical Methods and Computational Techniques in Electrical Engineering
Superpipelined high-performance optical-flow computation architecture
Computer Vision and Image Understanding
Accurate Optical Flow Sensor for Obstacle Avoidance
ISVC '08 Proceedings of the 4th International Symposium on Advances in Visual Computing
Automatic free parking space detection by using motion stereo-based 3D reconstruction
Machine Vision and Applications
Optimization strategies for high-performance computing of optical-flow in general-purpose processors
IEEE Transactions on Circuits and Systems for Video Technology
A hardware-friendly adaptive tensor based optical flow algorithm
ISVC'07 Proceedings of the 3rd international conference on Advances in visual computing - Volume Part II
A VLSI architecture and algorithm for Lucas-Kanade-based optical flow computation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fine grain pipeline architecture for high performance phase-based optical flow computation
Journal of Systems Architecture: the EUROMICRO Journal
High speed computation of the optical flow
ICIAP'05 Proceedings of the 13th international conference on Image Analysis and Processing
A multi-resolution approach for massively-parallel hardware-friendly optical flow estimation
Journal of Visual Communication and Image Representation
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This paper presents the implementation of an optical flow algorithm on a pipeline image processor. The overall optical flow computation method is presented and evaluated on a common set of image sequences. Results are compared to other implementations according to two different error measures. Due to its deterministic architecture, this implementation achieves very low computation delays that allow it to operate at standard video frame-rate and resolutions. It compares favorably to recent implementations in parallel hardware.