Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Pre-bond testable low-power clock tree design for 3D stacked ICs
Proceedings of the 2009 International Conference on Computer-Aided Design
A study of Through-Silicon-Via impact on the 3D stacked IC layout
Proceedings of the 2009 International Conference on Computer-Aided Design
Clock tree synthesis with pre-bond testability for 3D stacked IC designs
Proceedings of the 47th Design Automation Conference
TSV stress aware timing analysis with applications to 3D-IC layout optimization
Proceedings of the 47th Design Automation Conference
Clock tree embedding for 3D ICs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC
Proceedings of the 48th Design Automation Conference
Fault-tolerant 3D clock network
Proceedings of the 48th Design Automation Conference
Through-silicon-via management during 3D physical design: when to add and how many?
Proceedings of the International Conference on Computer-Aided Design
Stress-driven 3D-IC placement with TSV keep-out zone and regularity study
Proceedings of the International Conference on Computer-Aided Design
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This paper focuses on low-power clock network design for 3D ICs, where through-silicon vias (TSVs) form a regular 2-dimensional array. This TSV array style is shown to be more manufacturable and practical than layouts with TSVs located at irregular spots. However, due to limited TSV resources in TSV arrays, TSV utilization in a 3D clock network significantly affects the final clock power. A straightforward extension on existing works for TSV arrays cannot guarantee power efficiency. Therefore, we develop a decision-tree-based clock synthesis (DTCS) method to generate low-power and reliable clock networks by efficiently exploring the entire solution space for the best TSV array utilization. Our DTCS method has been applied for both gate-level chip-scale 3D clock designs and block-level global clock designs. Experimental results show that our algorithm effectively finds close-to-optimal solutions for power efficiency with skew minimization in short runtime. Our DTCS method achieves up to 13.5% average power reduction with more than 50% fewer TSVs compared with the straightforward extension on the existing algorithm.