Electric circuit analysis (2nd ed.)
Electric circuit analysis (2nd ed.)
Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
High-level current macro-model for power-grid analysis
Proceedings of the 39th annual Design Automation Conference
Demystifying 3D ICs: The Pros and Cons of Going Vertical
IEEE Design & Test
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
Simultaneous power and thermal integrity driven via stapling in 3D ICs
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
3D stacked power distribution considering substrate coupling
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC
Proceedings of the 48th Design Automation Conference
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3-D integration presents a path to higher performance, greater density, increased functionality and heterogeneous technology implementation. However, 3-D integration introduces many challenges for power and thermal integrity due to large switching currents, longer power delivery paths, and increased parasitics compared to 2-D integration. In this work, we provide an in-depth study of power and thermal issues while incorporating the physical design characteristics unique to 3-D integration. We provide a qualitative perspective of the power and thermal dissipation issues in 3-D and study the impact of Through Silicon Vias (TSVs) size for their mitigation. We investigate and discuss the design implications of power and thermal issues in the presence of decoupling capacitors, TSV/on-die/package parasitics, various resonance effects and power gating. Our study is based on a ten-tier system utilizing existing 3-D technology specifications. Based on detailed power distribution and heat dissipation models, we present a comprehensive analysis of TSV tapering for alleviating power and thermal integrity issues in 3-D ICs.