Physical Design for 3D System on Package
IEEE Design & Test
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Power and reliability management of SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reliability aware through silicon via planning for 3D stacked ICs
Proceedings of the Conference on Design, Automation and Test in Europe
A study of tapered 3-D TSVs for power and thermal integrity
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Reliable design of power distribution network for stacked integrated circuits introduces new challenges i.e., substrate coupling among through silicon vias (TSVs) and tiers grid in addition to reliability issues such as electromigration and thermo-mechanical stress, compared to conventional System on Chip (SoC). In this paper a comprehensive modeling of the TSV and stacked power grid with frequency dependent parasitic is proposed. The analytical model considers the impact of the substrate coupling between the TSVs and layers grid. A frequency domain based analysis flow is introduced to incorporate frequency dependent parasitics. The design of a reliable power distribution network is formulated as an optimization problem to minimize power noise under reliability and electromigration constraints. Experimental results demonstrate the efficacy of the problem formulation and solution technique.