Detecting Delay Flaws by Very-Low-Voltage Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
High volume microprocessor test escapes, an analysis of defects our tests are missing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Parametric Failures in CMOS ICs " A Defect-Based Analysis
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Screening MinVDD Outliers Using Feed-Forward Voltage Testing
ITC '02 Proceedings of the 2002 IEEE International Test Conference
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Handling inverted temperature dependence in static timing analysis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Worst-case performance prediction under supply voltage and temperature variation
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
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This work attempts to improve the commonunderstanding of multiple temperature testing bypresenting previously unpublished data as well asderiving a simple model for bounding an IC'sperformance within the three dimensional space definedby VDD, frequency, and temperature. The model is usedto design new temperature screens to improve theresolution between healthy and defective ICs.Temperature based test data is presented for Scan, LBIST,and TDF based MinVDD measurements as well astransistor characteristics needed to parameterize themodel. The test vehicles used are 0.25µm and 0.18µmCMOS ASICs fabricated by LSI Logic.