Neighborhood Selection for IDDQ Outlier Screening at Wafer Sort
IEEE Design & Test
Detection of Temperature Sensitive Defects Using ZTC
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Delay Defect Screening using Process Monitor Structures
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
The Impact of Multiple Failure Modes on Estimating Product Field Reliability
IEEE Design & Test
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Proceedings of the Conference on Design, Automation and Test in Europe
Estimation of fault-free leakage current using wafer-level spatial information
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Adaptive reduction of the frequency search space for multi-vdd digital circuits
Proceedings of the Conference on Design, Automation and Test in Europe
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In sub-micron CMOS processes, it has become increasingly difficult to identify and separate outliers from the intrinsic distribution at test. This is due to the increasing inadequacy of reliability screens such as burn-in and IDDQ testing. Statistical Post-Processing (SPP) methods have been developed to run off-tester using the raw data generated from Automatic Test Equipment (ATE) and wafersort maps. Post-Processing modules include advanced IDDQ tests such as Delta IDDQ and the Nearest Neighbor Residual (NNR), as well as other non-IDDQ based reliability-focused modules.This work presents the application and results of SPP at LSI Logic on 0.18um CMOS products. Challenges of production implementation have been overcome, which include "user definable" adaptive threshold limits, handling multiple data sources, and data flow management. Burn-in data and customer Defects per Million units (DPM) data show a 30-60% decrease in failure rate with SPP implementation with very acceptable yield loss.