Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2003 international symposium on Low power electronics and design
Discrete Vt assignment and gate sizing using a self-snapping continuous formulation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems)
Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems)
Temperature-insensitive synthesis using multi-vt libraries
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Proceedings of the 13th international symposium on Low power electronics and design
Temperature- and Voltage-Aware Timing Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the Scaling of Temperature-Dependent Effects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Traditionally, the effects of temperature on delay of CMOS devices have been evaluated using the highest operating temperature as a worst-case corner. This conservative approach was based on the fact that, in older technologies, CMOS devices systematically degraded their performance as temperature increases. With the progressive scaling of technology, however, there has been a continuous reduction of the gap between supply and threshold voltages of devices, mostly due to low-power constraints. The latter have accelerated this trend by using libraries containing multiple instances of a cell with different ranges of threshold voltages; in particular, the use of high-V"t cells to control sub-threshold leakage currents has made this gap smaller and smaller. The consequence of this trend is the occurrence of the so-called inverted temperature dependence (ITD), under which cells get faster as temperature increases. This new thermal dependence has made the old worst-case design approach obsolete, posing new EDA challenges. Beside complicating timing analysis, in particular, ITD has important and unforeseeable consequences for power-aware design, especially in dual-V"t logic synthesis. Due to a contrasting temperature dependence between low-V"t cells (which enjoy the classical, direct temperature dependence) and high-V"t cells (for which an inverted temperature dependence holds), a single-temperature worst-case design approach fails to generate netlists that are compliant with timing constraints for the entire temperature range. In this work, we first validate the relevance of ITD on an industrial 65nm CMOS multi-V"t library. Then, we describe an ITD-aware, dual-V"t assignment algorithm that guarantees temperature-insensitive operation of the circuits, together with a significant reduction of both leakage and total power consumption. The algorithm has been tested over standard benchmarks using three different replacement policies. Experimental results show an average leakage power savings of 50% w.r.t. circuits synthesized with a standard, commercial flow that does not take ITD into account and thus, to ensure that no temperature-induced timing faults occur, needs to resort to over-design (i.e., over-constraining the timing bound so as to make sure that temperature fluctuations never make the circuits violating the specified required time for all paths).