Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Introduction to algorithms
Precomputation-based sequential logic optimization for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Information theoretic measures of energy consumption at register transfer level
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Towards a high-level power estimation capability
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Architectural retiming: pipelining latency-constrained circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Finite state machine decomposition for low power
DAC '98 Proceedings of the 35th annual Design Automation Conference
Computational kernels and their application to sequential power optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Advanced compiler design and implementation
Advanced compiler design and implementation
Applied coding and information theory for engineers
Applied coding and information theory for engineers
Common-case computation: a high-level technique for power and performance optimization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Application-specific memory management for embedded systems using software-controlled caches
Proceedings of the 37th Annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Low Power Digital CMOS Design
Power Aware Design Methodologies
Power Aware Design Methodologies
Reconfigurable Low Energy Multiplier for Multimedia System Design
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
Telescopic units: a new paradigm for performance optimization of VLSI designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-level synthesis of low-power control-flow intensive circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Integrating variable-latency components into high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a high-level design methodology, called input space adaptive design, and new design automation algorithms for optimizing energy consumption and performance. Our techniques can be applied to behaviors described in hard-ware description languages, predesigned register-transfer level (RTL) circuits, or in the context of traditional high-level design methodologies. An input space adaptive design exploits the well-known fact that the quality of circuits can be significantly optimized by employing algorithms and implementation architectures that adapt to input statistics. This paper shows that harnessing the principles of input space adaptive design into a structured high-level design methodology can lead to large improvements in performance and energy consumption. We illustrate the tradeoffs involved in such designs, and demonstrate the need for a systematic design methodology in order to realize the full potential for performance and energy improvements. We propose a methodology for input space adaptive design that consists of the following steps: identification of parts of the behavior that hold the highest potential for optimization, selection of input subspaces whose occurrence can lead to significant reductions in implementation complexity, and transformation of the behavior to realize performance and/or energy savings. Evaluations of performance, energy, and area characteristics of input space adaptive designs in the context of a commercial high-level design flow indicate that such designs can reduce energy consumption by up to 58.9% (average of 40.0%), and simultaneously improve performance by up to 57.5% (average of 41.8%) compared to well-optimized designs that do not employ such techniques. The energy-delay product is reduced by up to 77.9% (average of 64.8%). When the performance improvements are translated into additional energy savings through supply voltage reduction, input space adaptive designs consume up to 74.2% (average of 68.8%) less energy at the same performance. The average area overhead is only 7.4%.