Exploiting instruction level parallelism in the presence of conditional branches

Profile-driven instruction level parallel scheduling with application to super blocks

Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture

Evaluation of scheduling techniques on a SPARC-based VLIW testbed

MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture

An integrated approach to accelerate data and predicate computations in hyperblocks

Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture

Attacking the semantic gap between application programming languages and configurable hardware

FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays

Performance-constrained pipelining of software loops onto reconfigurable hardware

FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays

Optimization of Machine Descriptions for Efficient Use

International Journal of Parallel Programming

Meta optimization: improving compiler heuristics with machine learning

PLDI '03 Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation

What can we gain by unfolding loops?

ACM SIGPLAN Notices

A Compiler Framework for Recovery Code Generation in General Speculative Optimizations

Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques

Superword-Level Parallelism in the Presence of Control Flow

Proceedings of the international symposium on Code generation and optimization

Compiling for EDGE Architectures

Proceedings of the International Symposium on Code Generation and Optimization

Global memory optimisation for embedded systems allowed by code duplication

SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems

Merging Head and Tail Duplication for Convergent Hyperblock Formation

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture

Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.264/AVC deblocking filter

Proceedings of the conference on Design, automation and test in Europe

Evaluating compiler technology for control-flow optimizations for multimedia extension architectures

Microprocessors & Microsystems

Genetic programming applied to compiler heuristic optimization

EuroGP'03 Proceedings of the 6th European conference on Genetic programming

Tree traversal scheduling: a global instruction scheduling technique for VLIW/EPIC processors

LCPC'01 Proceedings of the 14th international conference on Languages and compilers for parallel computing