Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
A programming environment for the design of complex high speed ASICs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Evaluation of the streams-C C-to-FPGA compiler: an applications perspective
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
A C-based synthesis system, Bach, and its application (invited talk)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Mapping a Single Assignment Programming Language to Reconfigurable Systems
The Journal of Supercomputing
System Design with SystemC
Behavioral Model Synthesis with Cones
IEEE Design & Test
Compiling Application-Specific Hardware
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Implementing C Algorithms in Reconfigurable Hardware Using C2Verilog
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Specifying and Compiling Applications for RaPiD
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
The Transmogrifier C hardware description language and compiler for FPGAs
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
HardwareC -- A Language for Hardware Design (Version 2.0)
HardwareC -- A Language for Hardware Design (Version 2.0)
ACM SIGPLAN Notices
The Challenges of Hardware Synthesis from C-Like Languages
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Optimized Generation of Data-Path from C Codes for FPGAs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Application Development on the SRC Computers, Inc. Systems
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01
A versatile, low latency HyperTransport core
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Synthesis of reconfigurable high-performance multicore systems
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Performance and power of cache-based reconfigurable computing
Proceedings of the 36th annual international symposium on Computer architecture
A Force-Directed Scheduling based architecture generation algorithm and design tool for FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
Neural Acceleration for General-Purpose Approximate Programs
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
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This poster describes CHiMPS, a toolflow that aims to provide software developers with a way to program hybrid CPU-FPGA platforms using familiar tools, languages, and techniques. CHiMPS starts with C and produces a specialized spatial dataflow architecture that supports coherent caches and the shared-memory programming model. The toolflow is designed to abstract away the complex details of data movement and separate memories on the hybrid platforms, as well as take advantage of memory management and computation techniques unique to reconfigurable hardware. This poster focuses on the memory design for CHiMPS, particularly the use of numerous small caches customized for various phases of program execution. The poster also addresses area vs. performance tradeoffs for various configurations. Applications compiled using CHiMPS show performance improvements of more than 36x on simple compute-intensive kernels, and 4.3x on the difficult-to-parallelize STSWM application without any special optimizations compared to running only on the CPU. The toolflow supports full ANSI-C, and produces hardware that runs on platforms that are expected to be available within one year