Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
A retargetable compiler for ANSI C
ACM SIGPLAN Notices
SUIF: an infrastructure for research on parallelizing and optimizing compilers
ACM SIGPLAN Notices
ACM Computing Surveys (CSUR)
High-level synthesis techniques for reducing the activity of functional units
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Synthesis of power-optimized and area-optimized circuits from hierarchical behavioral descriptions
DAC '98 Proceedings of the 35th annual Design Automation Conference
Advanced compiler design and implementation
Advanced compiler design and implementation
SpC: synthesis of pointers in C: application of pointer analysis to the behavioral synthesis from C
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
The Verilog hardware description language (4th ed.)
The Verilog hardware description language (4th ed.)
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Common-case computation: a high-level technique for power and performance optimization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
The Designer's Guide to VHDL
Verilog Designer's Library
Digital Image Processing Algorithms and Applications
Digital Image Processing Algorithms and Applications
IEEE Design & Test
A C to HDL Compiler for Pipeline Processing on FPGAs
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
The Transmogrifier C hardware description language and compiler for FPGAs
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PACT HDL: a compiler targeting ASICS and FPGAS with power and performance optimizations
Power aware computing
Automatic translation of software binaries onto FPGAs
Proceedings of the 41st annual Design Automation Conference
Leakage power optimization with dual-Vth library in high-level synthesis
Proceedings of the 42nd annual Design Automation Conference
A model-based extensible framework for efficient application design using FPGA
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Exploring power reduction options for a single-chip multiprocessor through system-level modeling
Journal of Embedded Computing - Issues in embedded single-chip multicore architectures
An overview of a compiler for mapping software binaries to hardware
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Force-Directed Scheduling based architecture generation algorithm and design tool for FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
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Chip fabrication technology continues to plunge deeper into sub-micron levels requiring hardware designers to utilize ever-increasing amounts of logic and shorten design time. Toward that end, high-level languages such as C/C++ are becoming popular for hardware description and synthesis in order to more quickly leverage complex algorithms. Similarly, as logic density increases due to technology, power dissipation becomes a progressively more important metric of hardware design. PACT HDL, a C to HDL compiler, merges automated hardware synthesis of high-level algorithms with power and performance optimizations and targets arbitrary hardware architectures, particularly in a System on a Chip (SoC) setting that incorporates reprogrammable and application-specific hardware. PACT HDL is intended for applications well suited to custom hardware implementation such as image and signal processing codes. By making the compiler modular and flexible, optimizations may be executed in any order and at different levels in the compilation process. PACT HDL generates industry standard HDL codes, such as RTL Verilog and VHDL, which may be synthesized and profiled for power using commercial tools. This is the first paper on the PACT compiler project in a series. The compiler framework and introductory optimizations are presented. Later papers will focus on these and other optimizations in detail.