High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Hitting the memory wall: implications of the obvious
ACM SIGARCH Computer Architecture News
Low-power architectural design methodologies
Low-power architectural design methodologies
Comparing models of computation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
A recursive algorithm for low-power memory partitioning
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Automatic data migration for reducing energy consumption in multi-bank memory systems
Proceedings of the 39th annual Design Automation Conference
System Design with SystemC
PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Improving memory energy using access pattern classification
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Application-driven processor design exploration for power-performance trade-off analysis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
ACM Transactions on Embedded Computing Systems (TECS)
ASAP '02 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
An Environment for Exploring Low Power Memory Configurations in System Level Design
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Modeling Embedded Systems and SoC's: Concurrency and Time in Models of Computation
Modeling Embedded Systems and SoC's: Concurrency and Time in Models of Computation
SystemC: methodologies and applications
SystemC: methodologies and applications
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Memory access scheduling and binding considering energy minimization in multi-bank memory systems
Proceedings of the 41st annual Design Automation Conference
SCMP: a single-chip message-passing parallel computer
The Journal of Supercomputing - Special issue: Parallel and distributed processing and applications
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Moore's law predicts that fabrication processes will soon yield over a billion transistors on a single die. Over the past twenty years, the gap between the amount of available real estate on a chip and designer productivity has widened and continues to grow, so that designers are less able to make effective use of the increasing number of transistors on a chip. The primary problem in system-on-a-chip (SoC) design is no longer the limit on the number of resources. Rather, the development of new methodologies and system-level design tools is the challenge that lies ahead, as these have become essential to keeping costs low in the planning and construction of these systems. Designers have realized that the consideration of the overwhelming details at register-transfer level (RTL) early in development restricts design space exploration, inhibits trade-off evaluation, and results in increased time-to-market. In order to effectively utilize the available resources, the entry point of design flows in recent methodologies is at higher levels of abstraction, with consideration to significantly fewer details of the final hardware implementation. In recent years, we have also seen the introduction of single-chip multiprocessors. As new tools and methodologies emerge for abstract system design, proposed solutions to the arising problems in the performance of single-chip multiprocessors can be implemented and evaluated more efficiently. For example, the amount of on-chip memory for such parallel systems continues to steadily rise, but so does the amount of power used by the memory system. In this work, we apply novel design methodology and tools to a single-chip multicore architecture, considering alternatives for power reduction of the storage components through system-level modeling.