Exploring power reduction options for a single-chip multiprocessor through system-level modeling
Journal of Embedded Computing - Issues in embedded single-chip multicore architectures
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In this paper, we present a novel design procedure for multi-module, multi-port memory design that satisfies area and/or energy/timing constraints. Our procedure consists of (i) use of Storage Bandwidth Optimization (SBO) techniques to simplify the conflict graph and (ii) use of memory exploration techniques to determine the best memory configuration (number of modules, size and number of ports per module) with the minimum area if the energy and timingare bounded or with the minimum energy/timing if the area is bounded. Here the simplest conflict graph implies more possibilities for the arrays assigned to the same module without the penalty in an increase of the number of ports for each module. Our benchmark shows that the heuristic algorithm is very efficient to decide the best memory configuration for the system constraints (timing, area, or energy). In addition, the CACTI tool [14] is modified to estimate the timing, area, and energy for each module in different CMOS technologies (0.8um. 0.35um, and 0.18um). Furthermore, we consider the lifetime for arrays; this results in the significant reduction in timing, area, and energy for the arrays executed in different cycles sharing the same memory module.