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ACM SIGPLAN Notices
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ACM SIGPLAN Notices
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ISLPED '95 Proceedings of the 1995 international symposium on Low power design
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DAC '98 Proceedings of the 35th annual Design Automation Conference
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DATE '99 Proceedings of the conference on Design, automation and test in Europe
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PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
IEEE Design & Test
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FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
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IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 14 - Volume 15
EURASIP Journal on Applied Signal Processing
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Recently, there has been a focus on high-level languages, C/C++ in particular, for hardware synthesis. At the same time, power dissipation is becoming an important metric in hardware design. This work presents PACT HDL, a C to HDL Compiler with facilities for power and performance optimizations. PACT HDL is an attempt to merge together automated hardware synthesis optimizations for power and performance with the capability to leverage high-level algorithms written in C and target arbitrary hardware architectures. By making the compiler modular and flexible, optimizations may be executed in any order and at different levels in the compilation process. PACT HDL generates HDL codes, such as RTL Verilog and VHDL that can be synthesized and profiled for power using commercial tools.