An optimum channel-routing algorithm for polycell layouts of integrated circuits
DAC '73 Proceedings of the 10th Design Automation Workshop
DAC '76 Proceedings of the 13th Design Automation Conference
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
DAC '82 Proceedings of the 19th Design Automation Conference
Geometrical compaction in one dimension for channel routing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
On improving channel routability
ACM SIGDA Newsletter
An Efficient Channel Routing Algorithm to Yield an Optimal Solution
IEEE Transactions on Computers
Novel routing schemes for IC layout part I: Two-layer channel routing
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Channel routing by constraint logic
SAC '92 Proceedings of the 1992 ACM/SIGAPP Symposium on Applied computing: technological challenges of the 1990's
A pin permutation algorithm for improving over-the-cell channel routing
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Power Optimization in VLSI Layout: A Survey
Journal of VLSI Signal Processing Systems
The future of logic synthesis and physical design in deep-submicron process geometries
Proceedings of the 1997 international symposium on Physical design
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Improved channel routing by via minimization and shifting
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
An industrial world channel router for non-rectangular channels
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A novel technique for sea of gates global routing
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Three-layer bubble-sorting-based nonManhattan channel routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An enhanced multilevel routing system
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A wire routing scheme for double-layer cell arrays
DAC '84 Proceedings of the 21st Design Automation Conference
DAC '84 Proceedings of the 21st Design Automation Conference
A hiererachical, error-tolerant compactor
DAC '84 Proceedings of the 21st Design Automation Conference
A switchbox router with obstacle avoidance
DAC '84 Proceedings of the 21st Design Automation Conference
Channel routing in Manhattan-diagonal model
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Manhattan-diagonal routing in channels and switchboxes
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Two-layer bus routing for high-speed printed circuit boards
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Algorithms for permutation channel routing
Integration, the VLSI Journal
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The channel routing problem is a special case of the wire routing problem when interconnections have to be performed within a rectangular strip having no obstructions, between terminals located on opposite sides of the rectangle. We present here a new channel routing algorithm, based on reduction of the problem to the case of a (2×n) grid and on consistent utilization of a “divide and conquer” approach. For the current implementation of the algorithm, the running time is proportional to N×n×log (m), where N is the number of nets, n is the length of the channel (number of columns) and m is the width of the channel (number of tracks). Traditional technological restrictions are assumed, i.e. net terminals are located on vertical grid lines, two wiring layers are available for interconnections - one layer is used exclusively for vertical segments, another for horizontal and vias are introduced for each layer change. This algorithm consistently outperforms several known routers in quality of wiring. We tested the algorithm on several benchmark problems. One of them - Deutsch's “difficult ex&le” - was routed with only 19 horizontal wiring tracks (the absolute minimum for this case), whereas all other known routers required 20 or more tracks.