DAC '83 Proceedings of the 20th Design Automation Conference
DAC '76 Proceedings of the 13th Design Automation Conference
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
DAC '82 Proceedings of the 19th Design Automation Conference
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
New placement and global routing algorithms for standard cell layouts
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Object oriented Lisp implementation of the CHEOPS VLSI floor planning and routing system
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A multi-layer channel router with new style of over-the-cell routing
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
An efficient routing algorithm for SOG cell generation on a dense gate-isolated layout style
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
HAL: heuristic algorithms for layout synthesis
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
EURO-DAC '90 Proceedings of the conference on European design automation
The star-routing algorithm based on Manhattan-Diagonal model for three layers channel routing
WSEAS Transactions on Circuits and Systems
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In the LSI chip layout design, channel routing is one of the key problems. The problem is to route a specified net list between two rows of terminals across a two layer channel. This paper presents a new routing algorithm, which is an improved version of the classical “left edge algorithm”. The new algorithm uses a row by row approach, calculating an optimum net assignment to each row. The algorithm was implemented for examples in previously published papers. Experimental results show that the new algorithm produces optimum solutions in most cases.