DAC '84 Proceedings of the 21st Design Automation Conference
Two-dimensional channel routing and channel intersection problems
DAC '82 Proceedings of the 19th Design Automation Conference
Pad placement and ring routing for custom chip layout
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Minimum-Congestion Hypergraph Embedding in a Cycle
IEEE Transactions on Computers
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The final step in the layout of integrated circuits involves connecting a central module to a surrounding ring of pads. Hence the region to be routed is in the shape of a moat. This paper presents a practical approach to the moat routing problem. The approach is based on an efficient channel routing algorithm with additional features addressing the characteristics of the moat configuration. While signal nets are similar to those of a channel router, power nets are routed in a single layer of metal. The geometry of the moat imposes some restrictions, but often allows additional compaction of the routes. Each side of the moat requires a different amount of space to complete the routing, and each side of the pad ring may be moved independently. This produces an asymmetrical moat, which minimizes chip area and guarantees 100 percent routing completion.