Pad placement and ring routing for custom chip layout

Authors:
Deborah C. Wang
Affiliations:
Department of Electrical Engineering and Computer Science, Electronics Research Laboratory, University of California, Berkeley, CA
Venue:
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Year:
1991

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Abstract

This paper presents an optimum scheme for interconnecting the chip core and the I/O pads in the final stage of physical design. The pad placement routine, based on linear assignment, determines the dimension of the pad ring and selects the optimum position for each pad with the objective of minimizing the chip area and the total wire length. The router is based on a channel routing algorithm which incorporates additional features to address the special needs of the ring configuration. It attempts to achieve 100% routing completion in a rectangular ring-shaped area with two interconnect layers. The complete package has been implemented as part of the BEAR Layout System for custom chip design.