DAC '83 Proceedings of the 20th Design Automation Conference
DAC '84 Proceedings of the 21st Design Automation Conference
A solution to line-routing problems on the continuous plane
DAC '69 Proceedings of the 6th annual Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
The “PI” (placement and interconnect) system
DAC '82 Proceedings of the 19th Design Automation Conference
Routing with a scanning window-8Ma unified approach
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
VIA minimization by layout modification
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
WEAVER: a knowledge-based routing expert
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
An industrial world channel router for non-rectangular channels
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An Efficient VLSI Switch-Box Router
IEEE Design & Test
DAC '84 Proceedings of the 21st Design Automation Conference
MOLE: a sea-of-gates detailed router
EURO-DAC '90 Proceedings of the conference on European design automation
A parallel dual-scanline algorithm for partitioning parameterized 45-degree polygons
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
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Detour is the channel router used by the Magic layout system. Based on Rivest and Fiduccia's “greedy” channel router, Detour is capable of routing switchboxes and channels containing obstacles such as preexisting wiring. It jogs nets around multi-layer obstacles such as contacts, and routes over single-layer obstacles. If there are no obstacles, results are comparable to other good channel routers. Detour thus combines the effectiveness of traditional channel routers with the flexibility of net-at-a-time routers.